This workshop will bring classical system architecture and design experts and AI/ML algorithmic experts together in one forum.
The goal is to brainstorm about challenges in designing secure and resilient AI-centric systems in general, but with a special
focus on autonomous systems (such as self-driving cars and industrial robots) – where safety and security are of paramount
The knowledge and expertise of classical mainframe and server architects who are experts in designing ultra-reliable and secure systems will be blended with domain experts in AI; particularly those with an established expertise in developing reliable and secure AI algorithms.
The organizers of this workshop largely represent the classical system architects with expertise in building robust and energy efficient systems. The program will be a blend of talks selected from submitted abstracts and invited speakers. The latter will largely feature experts in core AI algorithms, especially those focused on adversarial robustness, few-shot learning, immunity against catastrophic forgetfulness, etc.
This first workshop on SARA (Secure and Resilient Autonomy) will primarily focus on the safety, security and reliability aspects of AI-centric systems. Topics of interest include (but are not limited to):
Researchers in this field are encouraged to submit an extended abstract. We also encourage presentations showcasing prototype
demonstrations and open source contributions.
Submission site: https://easychair.org/conferences/?conf=sara2020
The workshop organizing committee has put together a program committee that will assist in selecting papers (abstracts) submitted to SARA. The program committee member names will be published online within the next couple of weeks.
|Time (CT)||Talk Title||Talk Category||Speaker(s)|
|9:00am||Workshop Introduction||Welcoming Remarks||Nandhini Chandramoorthy (IBM)|
|9:05am||To be announced||Keynote-I||Dr. Tom Rondeau (DARPA MTO)|
|9:50am||Coffee Break + Discussion|
|Morning Paper and Invited Talk Session: Chair – Karthik Swaminathan (IBM)|
|10:05am||Energy-Efficient Circuits for Entropy Generation and Secure Encryption||Invited Talk-I||Dr. Sanu Matthew (Intel Corp.)|
|10:25am||Feature Map Vulnerability Evaluation in CNNs||Accepted Paper||Abdulrahman Mahmoud (UIUC), Siva Kumar Sastry Hari (NVIDIA), Christopher Fletcher (UIUC), Sarita Adve (UIUC), Charbel Sakr (UIUC), Naresh Shanbag (UIUC), Pavlo Molchanov (NVIDIA), Michael Sullivan (NVIDIA), Timothy Tsai (NVIDIA), Stephen Keckler (NVIDIA)|
|10:40am||Reliable Intelligence in Unreliable Environment||Invited Talk-II||Dr. Saibal Mukhopadhyay (GeorgiaTech)|
|11:00am||Towards Information Theoretic Adversarial Examples||Accepted Paper||Chia-Yi Hsu (NCHU), Pin-Yu Chen (IBM), Chia-Mu Yu (NCHU)|
|11:15am||Explaining Away Attacks against Neural Networks||Accepted Paper||Sean Saito, Jin Wang (SAP Asia)|
|11:30am||Poster Presentations + Discussion|
|1:30pm||Poster Presentations + Discussion (contd.)|
|2:00pm||Towards Robust and Efficient Deep Learning Systems||Keynote-II||Prof. Xue Lin (Northeastern University)|
|Afternoon Paper and Invited Talk Session|
|2:45pm||MUTE: Data-Similarity Driven Multi-Hot Target Encoding for Neural Network Design||Accepted Paper||Mayoore Jaiswal, Bumsoo Kang, Jinho Lee, Minsik Cho (IBM)|
|3:00pm||WARDEN: Warranting Robustness against Deception in Data Centers||Accepted Paper||Hazar Yueksel, Ramon Bertran, Alper Buyuktosunoglu (IBM)|
|3:15pm||To be announced||Embedded Tutorial (Invited Talk-III)||Dr. Pen-Yu Chen (IBM)|
|3:45pm||Coffee Break + Discussion|
|4:00pm||Panel Session: Pin-Yu Chen (IBM), Xue Lin (Northeastern University), Sarita Adve (UIUC),
Akshay Deshpande (Soothsayer Analytics).
Moderator: Pradip Bose (IBM)
|5:00pm||Conclusion||Closing Remarks||Organizers (IBM)|
Pradip Bose is a Distinguished Research Staff Member and manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over thirty-six years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D. degree from University of Illinois at Urbana-Champaign.
Nandhini Chandramoorthy is a Research Staff Member at IBM T. J. Watson Research Center involved in Deep Neural Network ASIC design with techniques to improve reliable operation at very low supply voltages, and pre-RTL performance modeling tools for multi-core architectures. She holds a Ph.D. degree from Penn State University.
Augusto Vega is a Research Staff Member at IBM T. J. Watson Research Center involved in research and development work in the areas of highly-reliable power-efficient embedded designs, cognitive systems and mobile computing. He holds a Ph.D. degree from Polytechnic University of Catalonia (UPC), Spain.
Karthik Swaminathan is a Research Staff Member at IBM T. J. Watson Research Center. His research interests include power and resilience-aware architectures, domain-specific accelerators and emerging technologies in processor design. He is also interested in aspects related to reliability and energy efficiency, particularly in architectures for machine learning. He holds a Ph.D. degree from Penn State University.